microchip의 PIC용 MPLAB C 컴파일러에서 작업할 때, C 소스에서 특정 레지스터 값을
#pragma config FOCS = INITO67;
이런 형식으로 지정할 수 있다. 이렇게 설정 할 수 있는 항목과 값들은 특정 mcu 마다 다르며, 그 내용은 mplab c 컴파일러가 설치된 곳의 doc 디렉토리에서 도움말 화일을 참조하여 알 수 있다. 또는 mpasm 디렉토리의 해당 mcu의 *.inc 화일에서 참조 할 수 있다.
다음은 PIC18F45K20의 configuration Setting 이다.
;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Reset Voltage bits: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; HFINTOSC Fast Start-up: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-0007FFh) write-protected ; WRTB = OFF Boot Block (000000-0007FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;==========================================================================
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